1. Field of the Invention
The invention relates in general to a packaging method, and more particularly to a method of fabricating wafer level package.
2. Description of the Related Art
Along with the advance in electronic technology, high-tech electronic products become available in the market one after another. The main purpose of package industry is to support the research and development of electronic products and assure that the speed of semiconductor packages continues to increase, that the functions of the semiconductor packages are fully availed, and that the electronic products incorporating the semiconductor packages posses the advantages of slimness, lightweight and compactness. In order to meet these requirements, the development of the semiconductor packages is headed towards: increasing the number of input/output (I/O) pads, speeding the transmission of signals, boosting the power, shortening the pitches, increasing the connecting efficiency (the ratio of the size of the chip inside the package to the size of the package), lightening, thinning and miniaturizing the size. Apart from that, a package with good heat dissipation and multiple chips is also highly demanded.
Current markets of electronic products are focused on the feature of portability. For example, electronic products such as notebook computer and personal digital assistant (PDA) have gradually become indispensable electronic products to modern people. To be applicable to the high space density of mobile electronic products, the memory module needs to maintain high efficiency and stable quality. Therefore, how to reduce module space and yet remain high quality or even increase data transmission efficiency has become an imminent issue to be resolved. However, conventional chip level package technology is unable to meet the requirements of future technology, the current trend is headed towards wafer level package which possesses the advantages of low cost and high quality.
According to the technology of conventional chip level package, the chips are singulated from the wafer first and then the wafer is packaged using a molding compound and tested. The size of a packaged chip is larger than the size of a chip by 20%. According to the technology of wafer level package, the wafer is packaged and tested first before being singulated into chips, therefore the packaged chip has the same size with the chip. According to the technology of wafer level package, not only the size of memory module is reduced, but also the features of slimness, lightweight and compactness of portable electronic products can be satisfied. Besides, the circuit layout of wafer level package is shorter and thicker, thereby effectively increasing the bandwidth and stability of data transmission and reducing the loss of currents. Moreover, the wafer level package does not need the molding compound used in the technology of chip level package for the packing of plastics or ceramics, so that the heat generated by the chip is effectively dissipated, which is conducive to the resolution of heat dissipation problem of portable electronic products.
In terms of a conventional optical component, the circuit layout is mainly distributed on the front surface of the optical component, and the front surface is used for receiving external light source at the same time. When the optical component needs to be electrically connected to a substrate such as a substrate used for testing or a circuit board of an electronic product applying the same, the front surface of optical component is normally electrically connected to the substrate via wiring. The aforementioned method is applicable to the technology of chip level package, but is not applicable to the method of fabricating wafer level package. Therefore, how to apply the method of fabricating wafer level package to the aforementioned optical component so that the size is miniaturized, the data transmission is stabilized and the heat dissipation is enhanced has become an imminent challenge to be resolved.